1. Field of the Invention
The present invention relates to non-volatile memory devices and, more particularly, to methods of code programming read-only memory (ROM) semiconductor devices.
2. Description of Related Art
A non-volatile, semiconductor memory device is designed to securely hold data even when power is lost or removed from the memory device. The read-only memory (ROM) is a non-volatile memory device widely used in microprocessor-based digital electronic equipment for storing predetermined programs.
Arrays of memory cells are conventionally disposed in ROM devices for storing data, wherein each memory cell includes a transistor. These transistors, which typically comprise metal-oxide-semiconductor field effect transistors (MOSFETs), are disposed at intersecting bit lines and word lines of the memory device. Data bit values or codes held by these memory cell transistors are permanently stored in the physical or electrical properties of the individual memory cells. Generally speaking, a consequence of the non-volatile nature of a ROM is that data stored in the memory device can only be read.
The fixation of this xe2x80x9cread-onlyxe2x80x9d data into the ROM is performed during a code programming process at the original manufacture or fabrication of the memory device. Code programming a ROM typically entails ion implanting the read-only data into transistor channel regions of selected memory cells of the memory.
Since only the channel regions of only selected memory-cell transistors are ion implanted, other areas of the memory device should be covered and protected during the ion-bombardment step. Accordingly, code photomasks have been developed in the prior art for permitting the implantation of ions only into selected regions of the semiconductor. Usage of code photomasks during the code programming process has lead to the characterization of these memory devices as mask ROMs.
Regarding code photomasks, these tools for facilitating code programming of the mask ROM operate using principles of photolithography. Photolithography is a method of transferring a pattern onto a substrate so as to create structures down to the scale of fractions of a micron. A photolithography process can be incorporated, for example, in the fabrication of many modem devices such as MEMS (micro-electro-mechanical systems), optics, and semiconductor devices including mask ROMs.
A typical optical photolithographic process is implemented by depositing onto a substrate such as a semiconductor wafer, by some means (usually a spinner), a layer of photosensitive resist which can be patterned by exposure to ultraviolet (UV) light or another radiation type. To undergo exposure, the photoresist covered wafer is placed beneath a photomask designed to prevent the penetration of radiation through certain portions of the photoresist. Predetermined areas of the photoresist then undergo a degree of polymerization or depolymerization, which can be a function of the nature and extent of photoresist exposure to the radiation. A chemical bath known as a developer can then be used to dissolve parts of the photoresist which remain relatively depolymerized after the radiation by placing the wafer therein and allowing the wafer to be rinsed for a designated time period. Having received the pattern from the photomask, the layer of photoresist on the wafer is typically referred to as a layer of patterned photoresist.
A patterned photoresist layer can be created either on a bare wafer or on a number of previously generated layers of a wafer, with a limitation that the layer or layers should have somewhat planar surfaces to avoid problems including depth of focus variances. Common uses for patterned photoresist include selectively doping certain areas of a wafer while preventing other protected areas from being implanted, and selectively etching underlying layers on a substrate. When used as an implantation barrier, the patterned photoresist can prevent the underlying protected areas from receiving dopant, thereby allowing electrical properties of the substrate to differ between sites. When used as an etch barrier, the patterned photoresist can be functionally unaffected by the etching process, thereby protecting material under the patterned photoresist from being etched.
In certain process steps, it may be beneficial to utilize two consecutively stacked layers of photoresist, with each of the two photoresist layers having a distinct and separate pattern. According to such a construction, certain areas of the substrate can be covered by both photoresist layers, while other areas are covered only partially by a single photoresist layer or not covered at all. When utilizing double photoresist layers, however, a tendency can exist for the first photoresist layer to become softened (depolymerized) during exposure of or to the second photoresist layer. Other problems that may occur with the first photoresist layer include wrinkling due to an additional bake step in connection with processing of the second photoresist layer, loss of dimensional integrity, and the dissolving of portions of the first layer when the substrate is subjected to a developer for the second time. These shortcomings may have the undesirable effect of creating a larger process window and, consequently, may decrease the resolution of the photoresist.
As an alternative solution which may avoid the aforementioned difficulties, prior-art photolithography approaches typically utilize an oxide layer in combination with one or more photoresist layers. For example, an oxide layer can be positioned beneath a second photoresist layer, in place of the first photoresist layer. Implementation of the oxide layer can achieve desired etching and implanting goals in accordance with circuit fabrication objectives without many of the above-discussed problems. Known shortcomings are presented in connection with fabrication processes utilizing oxide layers instead of the first photoresist patterns, as well. For instance, further processing steps are required to pattern the oxide layers, which steps can lead to increased processing times, consumption of additional materials, and augmented costs. Undesirable particles can also be introduced during the oxide deposition and during the oxide patterning process. Furthermore, implementation of an oxide pre-code masking process may induce a critical dimension (CD) bias, and may cause etch uniformity related issues. Imprecise CD control during formation of a pre-code pattern in an oxide layer can adversely affect the real-code implantation process. In the context of mask ROM fabrication and coding, it is desirable to code program the memory devices as quickly and simply as possible, with a minimal expenditure of resources and a minimal risk of adverse particle introduction and CD bias.
A need thus exists in the prior-art for methods of manufacturing mask ROMs in which processing times and materials can be attenuated, to thereby reduce costs. A need also exists for reliable code programming methods which can decrease the potential for particle contamination during the pre-code steps. Furthermore, with device sizes approaching the resolution limit of optical photolithography, wherein, for example, a code implantation area may be 0.15 um2, a need continues in the prior-art to exercise precise pre-code and real-code CD control to thereby maintain device performance in a cost effective manner.
The present invention addresses these needs by providing, in accordance with one aspect, non-volatile memory coding structures and methods for making the same which can be fast, clean, controlled, and simple in construction. The invention disclosed herein provides a method of code programming a mask ROM, wherein a negative photoresist is placed over word lines of the ROM and patterned to thereby form the ROM pre-code pattern directly in the negative photoresist. The negative photoresist is then hardened to enable the forming of a second layer of photoresist directly on the negative photoresist, wherein the second layer of photoresist is patterned to comprise ROM real-code openings for facilitating a subsequent code-programming implantation step. In accordance with another aspect of the invention, a positive photoresist is used instead of the negative photoresist.
To achieve these and other advantages and in accordance with a purpose of the invention, as embodied and broadly described herein, the invention provides a method of code programming a ROM device having implanted bit lines disposed beneath and intersecting with word lines, and having a gate oxide layer disposed between the bit lines and the word lines. The method comprises a step of forming a first photoresist layer, which can be a negative photoresist, over the word lines and the gate oxide layer. The first photoresist layer is patterned to develop pre-code openings over all of the memory cells which may be candidates for coding, and then hardened using either a treatment implant or a treatment plasma. Subsequently, a second photoresist layer is formed over the first photoresist layer and patterned to develop real-code openings over memory cells which are to be coded with for example a logic xe2x80x9c0xe2x80x9d value. Each memory cell to be coded is then implanted with particles passing through the pre-code and the real code openings and into the memory cells. The first photoresist layer can be a positive photoresist in other embodiments.
According to one aspect of the invention, a method of fabricating a semiconductor device structure is provided, comprising the steps of depositing an anti-reflective coating (ARC) on a substrate; placing a photoresist layer on the ARC, wherein the ARC is sandwiched between the substrate and the photoresist layer, a disposition of the photoresist layer over the ARC being such that no patterned layers sufficient to block a code implant of the semiconductor device are present between the photoresist layer and the ARC; forming a pattern into the photoresist layer; and treating the photoresist layer using at least one of an incident beam of implants and a plasma.
In one implementation of the present invention, the photoresist layer comprises a first photoresist layer, the pattern comprises a pre-code pattern, and the substrate comprises a polysilicion word line. The method can further comprise the steps of storing the semiconductor device in a storage location; retrieving the semiconductor device from the storage location; forming a second photoresist layer over the first photoresist layer; selectively exposing the second photoresist layer to define a real-code pattern therein; and implanting particles through openings in the real-code pattern and into the substrate. The treatment implants can comprise a 10 Kev to 50 Kev 1E15 to 5E15 dose Ar or N2 implant. The first photoresist layer comprises openings corresponding to the pre-code pattern, and the second photoresist layer comprises openings corresponding to the real-code pattern. The pre-code openings are greater in number than the real-code openings; and a plurality of the real-code openings are aligned with a corresponding plurality of the pre-code openings. The treatment implants pass through the aligned real-code openings and into portions of the substrate to be code programmed. In accordance with one aspect, the semiconductor device comprises a mask ROM and the implanting step implants impurities into channels of selected memory cell transistors, so that those selected memory cell transistors have electrical properties corresponding to a logic xe2x80x9c0xe2x80x9d value.
In accordance with another aspect of the invention, the step of retrieving the semiconductor device can be performed after receipt of a customer order for a purchase of the semiconductor device; and the method can further comprise a step of removing the first and second layers of photoresist using a plasma ashing process such as O2 plasma ashing.
According to still another aspect of the present invention, an intermediate-processing structure of a ROM device comprises a semiconductor substrate; a plurality of parallel implanted bit lines, the implanted bit lines being oriented in a first direction; a gate oxide layer above the semiconductor substrate; a plurality of word lines formed above the gate oxide layer, the word lines being oriented in a second direction; and a patterned photoresist layer over the word lines and the gate oxide layer, the patterned photoresist layer having ROM pre-code openings positioned between adjacent bit lines and further being treated using at least one of a treatment implant and a treatment plasma. A disposition of the patterned photoresist layer over the word lines is such that no patterned layers sufficient to block a code implant of the ROM are present between the patterned photoresist layer and the word lines. The patterned photoresist layer can comprise a negative photoresist material. In other embodiments, the patterned photoresist layer can comprise a positive photoresist material.
In one aspect of the invention, the patterned photoresist layer can comprise a first photoresist layer; and the intermediate-processing structure can further comprise a second photoresist layer disposed over the first photoresist layer and being patterned to comprise ROM real-code openings therein, and particles implanted into channel regions of the semiconductor substrate, wherein positions of the implanted particles correspond to aligned openings extending through both the pre-code openings and the real-code openings. An ARC can be disposed between the first photoresist layer and the word lines; and the particles can comprise implants which have been implanted through the real-code openings, through corresponding word lines and into the channel regions of the semiconductor substrate between adjacent bit lines. The word lines can comprise polysilicon; the first photoresist layer can be treated with treatment implants; the substrate can comprises a semiconductor substrate having a P type background impurity; the bit lines can be formed of N type impurity; and the implanted ions in the substrate between adjacent bit lines can comprise P type impurity.
Accordance to another aspect of the present invention, a semiconductor ROM structure comprises at least one word line; and a photoresist layer disposed over at the least one word line, the photoresist layer comprising a ROM pre-code pattern and being treated using at least one of an incident beam of implants and a plasma hardener, a disposition of the photoresist layer over the at least one word line being such that no patterned layers sufficient to block a code implant of the ROM are present between the photoresist layer and the at least one word line.
In accordance with yet another aspect of the present invention, a semiconductor device structure comprises a substrate; an anti-reflective coating (ARC) disposed on the substrate; a first photoresist layer disposed on the ARC, the first photoresist layer comprising a first pattern having first openings and being treated using at least one of an incident beam of implants and a plasma, wherein the ARC is sandwiched between the substrate and the first photoresist layer, a disposition of the first photoresist layer over the ARC being such that no patterned layers sufficient to block a code implant of the semiconductor device are present between the photoresist layer and the ARC; and a second photoresist layer disposed on the first photoresist layer and comprising a second pattern having second openings.
Any feature or combination of features described herein are included within the scope of the present invention provided that the features included in any such combination are not mutually inconsistent as will be apparent from the context, this specification, and the knowledge of one of ordinary skill in the art. Additional advantages and aspects of the present invention are apparent in the following detailed description and claims.